<!doctype html><html lang=en><head><meta charset=utf-8><meta name=viewport content="width=device-width,initial-scale=1,viewport-fit=cover"><base href=https://www.lowrisc.org><link rel=icon type=image/png sizes=32x32 href=/favicon.png><title>Tagged memory tests &middot; lowRISC: Collaborative open silicon engineering</title><link href=/main.21c9d.css rel=stylesheet><script type=application/javascript>var doNotTrack=false;if(!doNotTrack){(function(i,s,o,g,r,a,m){i['GoogleAnalyticsObject']=r;i[r]=i[r]||function(){(i[r].q=i[r].q||[]).push(arguments)},i[r].l=1*new Date();a=s.createElement(o),m=s.getElementsByTagName(o)[0];a.async=1;a.src=g;m.parentNode.insertBefore(a,m)})(window,document,'script','https://www.google-analytics.com/analytics.js','ga');ga('create','UA-53520714-1','auto');ga('send','pageview');}</script></head><body><header><nav class="navbar navbar-expand-md navbar-light"><div class=container><a class=navbar-brand href=#><img src=/img/logo/logo-dualcolor.svg alt=lowRISC></a>
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<span class=navbar-toggler-icon></span></button><div class="collapse navbar-collapse" id=navbarCollapse><ul class="navbar-nav ml-auto"><li class=nav-item><a href=/our-work class=nav-link>Our work</a></li><li class=nav-item><a href=/open-silicon class=nav-link>Open Silicon</a></li><li class=nav-item><a href=/community class=nav-link>Community</a></li><li class=nav-item><a href=/blog class=nav-link>Blog</a></li><li class=nav-item><a href=/jobs class=nav-link>Jobs</a></li><li class=nav-item><a href=/about class=nav-link>About us</a></li><li class=nav-item><a class="btn lr-navbar-btn-gh" href=https://github.com/lowrisc>GitHub</a></li></ul></div></div></nav></header><main role=main><div class=container><h1>Tagged memory tests</h1><p>The original Rocket chip repository provides a thorough test suite for
the RISC-V ISA
(<a href=https://github.com/riscv/riscv-tests/tree/master/isa><code>riscv-tools/riscv-tests/isa</code></a>). All
tests are written in assembly.</p><p>A new test case is provided in <a href=https://github.com/lowRISC/riscv-tests/tree/master/isa/rv64si/ltag.S><code>riscv-tools/riscv-tests/isa/rv64si/ltag.S</code></a></p><p>More complicated tests can be found in
<a href=https://github.com/lowRISC/lowrisc-tag-tests/tree/master/tests><code>riscv-tools/lowrisc-tag-tests/tests</code></a>:</p><ul><li><code>tag_ld_st.cc</code> - Verifies a long sequence of random tag writes</li><li><code>parity.cc</code> - Random data is allocated on the heap. All the tag bits are then set by generating a number of different parity bits. Finally, all data is read back together with the corresponding tag bits and the parity bits are validated.</li></ul><h3 id=running-the-tests:d6b9ed3b04ae1eeb27ae38c643cd653d>Running the tests</h3><p>The tests can be run using the proxy kernel or within RISC-V
Linux. You can generate the proxy kernel executables using the
Makefile included (simple type <code>make</code>) or <code>make linux</code> to generate
binaries for RISC-V Linux.</p><p>The detailed steps necessary to run the tests in simulation or on the FPGA are
described in the subsequent sections of the tutorial.</p></div></main><footer class=lr-footer><div class=container><div class=row><div class="col-lg-2 d-none d-lg-block"><img src=/img/logo/logo-dualcolor.svg width=150px></div><div class=col><p>The text content on this website is licensed under a <a href=https://creativecommons.org/licenses/by/4.0/>Creative Commons Attribution 4.0 International License</a>, except where otherwise noted. No license is granted for logos or other trademarks. Other content &copy; lowRISC Contributors.</p><a href=/privacy-policy>Privacy and cookies policy</a>
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